杨兴华

点击数:   更新日期: 2021-05-10



杨兴华   讲师



电子邮箱: yangxh@bjfu.edu.cn

办公电话: 010-62336150


研究方向


1) 近似计算电路系统设计

2) 面向机器学习的高性能低功耗电路系统设计



教育工作经历


2020.9-至今，江南的注册网址理学院，讲师

2017.7-2020.9，华为技术有限公司北京研究所，高级工程师

2011.9-2017.6，清华大学电子工程系，电子科学与技术，博士

2007.9-2011.6，北京邮电大学电子工程学院，电子信息科学与技术专业，学士



主讲课程


《传感器电子学》、《人工智能基础》、《高频电子电路》、《FPGA实践》



奖励及荣誉称号


无



学术/社会兼职


无



工作及成果展示


发表论文：

[1] Yang X, Xing Y, Qiao F, et al. Multistage Latency Adders Architecture Employing Approximate Computing[J]. Journal of Circuits, Systems and Computers, 2017, 26(03): 1750039. (SCI收录, 检索号: EE5SF，影响因子：0.308)

[2] Yang X, Huang N, Chen Y, et al. A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing[J]. IEICE Electronics Express, 2016, 13(23): 20160990.(SCI收录, 检索号: EG4KD，影响因子：0.344)

[3] Wu Y, Yang X, Plaza A, et al. Approximate Computing of Remotely Sensed Data: SVM Hyperspectral Image Classification as a Case Study[J]. IEEE Journal of Selected Topics in Applied Earth Observations & Remote Sensing, 2016, 9:1-13. (SCI收录, 检索号: EH0QN，影响因子：2.145)

[4] Yang X, Qiao F, Liu C, et al. Design of multi-stage latency adders using detection and sequence-dependence between successive calculations[C]//Circuits and Systems (ISCAS), 2014 IEEE International Symposium on. IEEE, 2014: 998-1001. (EI收录,检索号: 20143818165266)

[5] Yang X, Qiao F, Liu C, et al. Design of variable latency adder based on present and transitional states prediction[C]//Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on. IEEE, 2013: 120-125. (EI收录, 检索号: 20140517239230)

[6] Yang X, Xing Y, Qiao F, et al. Approximate Adder with Hybrid Prediction and Error Compensation Technique[C]//VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on. IEEE, 2016: 373-378. (EI收录, 检索号: 20164002870943)

[7] Liu C, Yang X, Qiao F, et al. Design methodology for approximate accumulator based on statistical error model[C]//Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific. IEEE, 2015: 237-242. (EI收录, 检索号: 20151500728205)

[8] Chen Y, Yang X, Qiao F, et al. A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis[C]//VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on. IEEE, 2016: 385-390. (EI收录, 检索号: 20164002870945)


专利：“一种可变延时预测方法及基于预测的可变延时加法器”，公开。